Platforms
ocrypto is a tiny crypto library for 32-bit microcontrollers. It is partially written in portable C code, and partially in assembly code. The assembly part speeds up cryptographic operations even beyond the speed-up from our algorithmic improvements. The desired variant of the assembly code is chosen as a build option, and is available for the most common microcontroller cores:
| Instruction Set Architecture | Processor Cores (Examples) |
| ARMv5-TE | ARM9E-S, ARM9EJ-S |
| ARMv6 | ARM1176 (e.g., as on Raspberry Pi Zero) |
| ARMv6-M | Cortex-M0/M0+ |
| ARMv7-M | Cortex-M3 |
| ARMv7E-M | Cortex-M4/M7 (two variants: with/without FPU) |
| ARMv8-M Baseline | Cortex-M23 |
| ARMv8-M Mainline | Cortex-M33/M35P/M55/M85 (four variants: with/without DSP, with/without FPU) |
| ARMv7-A | Cortex-A7 |
| ARMv8-A (T32) | Cortex-A53/72 (e.g., as on Raspberry Pi 3/4 Model B using a 32-bit OS) |
| MIPS32 R2 to R5 | MIPS 4K/24K (works for both little- and big-endian processors) |
| MIPS32 R2 to R6 with DSP | MIPS microAptiv, MIPS 24KE (works for both little- and big-endian processors) |
For maximum portability, the C code in ocrypto conforms to the C89 standard. Supported compilers/assemblers are GCC, and for Cortex-M additionally Keil and IAR.
A generic reference implementation in pure C code is also available, which is portable to any device with a suitable C compiler. It provides only algorithmic optimizations, no device-specific optimizations. In addition, two other pure C variants are available that include optimizations specifically for RISC-V ISA variants:
| Target Architecture for C Code | Processor Cores (Examples) |
| RISC-V (RV32IM) | SiFive FE310 |
| RISC-V (RV32IMZbb) | Renesas core (e.g., as in R9A02G021) |
| Any (non-optimized generic code) | Any |